1. Field of the Invention
The present invention relates to the field of integrated circuits and integrated circuit packaging.
2. Prior Art
Present day 2D Monolithic ICs require discrete devices, such as capacitors, resistors and inductors, at the board level for correct operation. In general, two IC package pinouts are needed for electrical connection to each discrete device. As an example, an IC that needs to connect to 5 capacitors will need 10 extra pinouts. This increased pinout count increases IC package cost, IC area and board space. Additionally, it could degrade overall electrical performance because of the introduction of parasitic capacitance and possibly leakage current and noise.
As an example, certain of the assignee's multi-media IC products need bypass, flying and holding discrete capacitors. When put on a printed circuit board, each of these discrete capacitors needs two additional pinouts on the IC. Unfortunately these discrete capacitors are between 0.1 to 1.0 μF and are much larger in value compared to those utilized in typical CMOS and BiCMOS ICs (few fF). As such, these large value capacitors cannot be integrated in the standard 2D IC products utilizing standard technology available in the marketplace, such as foundries etc.
Despite all the difficulties, the need to integrate these and other board level discrete devices with the IC in one package is very real. Some manufacturers are now finding new ways of doing this. One such method is Linear Technology's “μmodule” technology, wherein individual packages are stacked using solder bumping for the interconnections. In another method of integration, the IC is bumped on top of a larger “passives chip”.
Unfortunately, both these techniques have disadvantages because the resulting package is large and therefore costly, and because chip-to-chip bump technology is very costly. Additionally, in the second method, the area of the passives chip is much larger than the area of the bumped chip on top of it, and an additional IC array connected thereto needs additional space, and a ROM array connected thereto needs additional space, making the package very large and with lots of in-and-out of chip interconnects. Whenever the “passive” chip and the active chip (IC) are either of different sizes, or when the device yields per wafer is low, wafer-to-wafer packaging techniques are not practical.